Studies on underfilling components with area array solder terminals in surface mount technology

The undertilling of CSP and BGA components with area array lead free and lead containing solder terminals in surface mount technology has been systematically studied and evaluated. One of the goals of the research was to definc the particular requirements that have to be put on CSPIBGA underfill materials and to estimate what level of process reliability for undertilling can be achieved. The knowledge and experience with flip chip undertilling could not be directly transferred to CSP and BGA assemblies duc to the differences in matcrial combinations and geometry of the joint gap as well as the differences in the nature and magnitude of the stress. Ageing and stress tcsts on test assemblies with commcrcially available and altemative undertill materials highlighted the specific advantages of undertilling CSPs and BGAs. The experimental findings and the simulations results allowed the required property profiles of CSPIBGA underfillers to be defined. From the effects of underfill defects, statements about process reliability could be made.