Gate delay time evaluation structure for deep-submicron CMOS LSIs

Author

Nishimura, Kazuyoshi ; Urano, Masami ; Ino, Masayuki ; Takeya, Ken ; Ishihara, Takuya ; Kado, Yuichi ; Inokawa, Hiroshi

Author_Institution

NTT LSI Labs., Atsugi, Japan

fYear

1996

fDate

25-28 Mar 1996

Firstpage

135

Lastpage

138

Abstract

A new test structure for gate delay time measurement has been developed. The delay times of over several tens of gate chain circuits can be measured efficiently. This structure has common input buffers, output buffers, and a selector to avoid signal skew between each gate chain circuit. The performance of a quarter-micron SIMOX CMOS and BULK CMOS device were measured and compared with this structure

Keywords

CMOS integrated circuits; SIMOX; delays; integrated circuit testing; large scale integration; time measurement; 0.25 micron; bulk CMOS device; deep-submicron CMOS LSI; gate chain circuit; gate delay time measurement; quarter-micron SIMOX CMOS device; test structure; Circuits; Delay effects; Frequency; Large scale integration; Power dissipation; Power measurement; Ring oscillators; Semiconductor device measurement; Testing; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1996. ICMTS 1996. Proceedings. 1996 IEEE International Conference on

Conference_Location

Trento

Print_ISBN

0-7803-2783-7

Type

conf

DOI

10.1109/ICMTS.1996.535634

Filename

535634

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2712747