An electrical signal disturbance detector and compressor based on FPGA platform

This paper presents a prototype system used to detect and compress disturbances commonly found in electrical signal, on both voltage and current. The algorithm for detecting and compressing the disturbances are synthesized in FPGA platform. The compression algorithm operates in three different stages: the innovation stage, the wavelet stage and the bit compression stage. These three stages provide efficient compression rate. Beside the algorithm description, the paper presents details of the hardware implementation and results obtained from synthetized and real signals.