A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues

Author

Nii, Koji ; Tsukamoto, Yasumasa ; Ishii, Yuichiro ; Yabuuchi, Makoto ; Fujiwara, Hidehiro ; Okamoto, Kazuyoshi

Author_Institution

Renesas Electron. Corp., Tokyo, Japan

fYear

2012

fDate

19-22 Nov. 2012

Firstpage

246

Lastpage

251

Abstract

We discuss dynamic read and write stabilities of embedded SRAMs in 28-nm high-k/metal-gate (HK/MG) bulk CMOS technology. Test chips which include 1-Mbit single-port SRAM and 512-kbit dual-port SRAM macros are designed and fabricated. A Good correlation for minimum operating voltage (V_min) between simulation and measurement is observed. We also introduce the test screening circuitry which takes the dynamic stability into consideration. We obtain the appropriate screening results from the evaluations of the testchip. It is also confirmed assured screening with 2.0% dynamic stability fault detection for an SoC product.

Keywords

CMOS integrated circuits; SRAM chips; circuit stability; integrated circuit technology; system-on-chip; HK/MG single-port SRAM; SoC product; dual-port SRAM; dynamic read-and-write stability; dynamic stability; embedded SRAM; fault detection; high-k/metal-gate bulk CMOS technology; minimum operating voltage; size 28 nm; storage capacity 1 Mbit; storage capacity 512 Kbit; test screening circuitry; Circuit stability; Clocks; Delay; Random access memory; Stability analysis; Temperature measurement; Vectors; 28nm; 6T; 8T; Dynamic stability; Read/Write disturb; SRAM; dual-port; high-k/metal-gate; single-port;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (ATS), 2012 IEEE 21st Asian

Conference_Location

Niigata

ISSN

1081-7735

Print_ISBN

978-1-4673-4555-2

Electronic_ISBN

1081-7735

Type

conf

DOI

10.1109/ATS.2012.59

Filename

6394209