MPEG1 and MPEG2 system layer implementation trade-off between micro coded and FSM architecture

Author

Froidevaux, Michel ; Gentit, Jean Marc

Author_Institution

Thomson Consumer Electron. Components, Meylan, France

fYear

34851

fDate

7-9 Jun1995

Firstpage

250

Lastpage

251

Abstract

In the context of digital consumer applications, it has been necessary to develop a parser handling the MPEG1 and MPEG2 system layer. This application is embedded either in the front end of audio, or video decoders, or as a back end of demultiplexer serving these applications. It works at 24 MHz and is implemented in 0.5 micron technology. Micro coded (MC) and finite state machine (FSM) architecture have been evaluated in detail, in order to manage trade-offs including flexibility, performance, development time, area versus timing or area versus scheduling

Keywords

consumer electronics; decoding; demultiplexing equipment; digital communication; digital signal processing chips; finite state machines; firmware; grammars; video equipment; video signal processing; 0.5 mum; 24 MHz; FSM architecture; MPEG1 system layer implementation; MPEG2 system layer implementation; area; audio decoder; back end; demultiplexer; development time; digital consumer applications; flexibility; front end; micro coded architecture; parser; performance; scheduling; timing; video decoders; Assembly; Automata; Automatic control; Communication system control; Consumer electronics; Decoding; Project management; Tellurium; Testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 1995., Proceedings of International Conference on

Conference_Location

Rosemont, IL

Print_ISBN

0-7803-2140-5

Type

conf

DOI

10.1109/ICCE.1995.517974

Filename

517974