• DocumentCode
    2718960
  • Title

    Register-sensitive software pipelining

  • Author

    Dani, Amod K. ; Ramanan, V. Janaki ; Govindarajan, R.

  • Author_Institution
    Veritas Software India Pvt. Ltd., Pune, India
  • fYear
    1998
  • fDate
    30 Mar-3 Apr 1998
  • Firstpage
    194
  • Lastpage
    198
  • Abstract
    We propose an integrated approach for register-sensitive software pipelining. In this approach, the heuristics proposed in the stage scheduling method of A.E. Eichenberger and E.S. Davidson (1995) are integrated with the iterative scheduling method to obtain schedules with high initiation rate and low register requirements. The performance of our integrated software pipelining method was analyzed for a large number of loops taken from a variety of scientific benchmark programs. Our studies reveal that the stage scheduling heuristics facilitate better performance benefits when applied at the scheduling time, resulting in significant performance improvement over both the stage scheduling method and the slack scheduling method
  • Keywords
    parallel programming; parallelising compilers; pipeline processing; scheduling; heuristics; initiation rate; integrated approach; integrated software pipelining method; iterative scheduling method; performance improvement; register requirements; register-sensitive software pipelining; scheduling time; scientific benchmark programs; slack scheduling method; stage scheduling heuristics; stage scheduling method; Educational institutions; Iris; Iterative methods; Modems; Pipeline processing; Scheduling algorithm; Supercomputers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing Symposium, 1998. IPPS/SPDP 1998. Proceedings of the First Merged International ... and Symposium on Parallel and Distributed Processing 1998
  • Conference_Location
    Orlando, FL
  • ISSN
    1063-7133
  • Print_ISBN
    0-8186-8404-6
  • Type

    conf

  • DOI
    10.1109/IPPS.1998.669910
  • Filename
    669910