Current integrating receivers for high speed system interconnects

Author

Sidiropoulos, Stefanos ; Horowitz, Mark

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1995

fDate

1-4 May 1995

Firstpage

107

Lastpage

110

Abstract

This paper presents a high speed receiver design that utilizes current integration in order to increase its noise immunity. The integration of current on a capacitor based on the incoming signal voltage effectively averages the incoming signal over its valid time period, therefore filtering out high frequency noise. An experimental design illustrating the concept has been fabricated in a 1.2 μm CMOS technology. The receiver dissipates 2.7 mW of power operating from a 5-V supply, achieves error free operation at a clock frequency of 250 MHz, and occupies 60×450 μm² of silicon area

Keywords

CMOS integrated circuits; VLSI; analogue-digital conversion; application specific integrated circuits; integrated circuit interconnections; integrating circuits; multiprocessor interconnection networks; receivers; 1.2 micron; 2.7 mW; 250 MHz; 5 V; CMOS technology; clock frequency; current integrating receivers; error free operation; high speed receiver design; high speed system interconnects; incoming signal voltage; memory interfaces; multiprocessor interconnection networks; noise immunity; valid time period; CMOS technology; Capacitors; Clocks; Filtering; Frequency; Sampling methods; Switches; Switching circuits; Voltage; Voting;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518147

Filename

518147