A scalable pipelined architecture for fast buffer SRAM´s

Author

Nicol, C.J. ; Dickinson, A.G.

Author_Institution

AT&T Bell Labs., Holmdel, NJ, USA

fYear

1995

fDate

1-4 May 1995

Firstpage

147

Lastpage

150

Abstract

The design of large synchronous buffer SRAMs for packet switching and signal processing applications is described. Called Scalable Cellular RAM (SCRAM), the approach configures memory blocks in a 2-D array with fully pipelined address and data distribution. The memory is scalable in that the access frequency is determined by the access time of a single block and is independant of the number of blocks. An experimental 0.5 μm CMOS 256 Kb SCRAM chip is described that operates at 240 MHz. Simulation results show that larger arrays are feasible using the suggested power reduction techniques

Keywords

CMOS memory circuits; SRAM chips; buffer storage; cellular arrays; integrated circuit design; memory architecture; packet switching; 0.5 micron; 240 MHz; 256 Kbit; 2D array; CMOS; SCRAM; access frequency; access time; fast buffer SRAM; memory blocks; packet switching; pipelined data distribution; power reduction techniques; scalable cellular RAM; scalable pipelined architecture; signal processing applications; synchronous buffer; Array signal processing; Clocks; Decoding; Delay; Frequency; Packet switching; Random access memory; Read-write memory; Signal design; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518155

Filename

518155