Efficient Implementation of AES Algorithm in FPGA Device

This paper presents an efficient FPGA implementation approach of the Advanced Encryption Standard (AES) Algorithm. The architectural optimization has been incorporated which includes pipelining techniques. Speed is increased by processing multiple rounds simultaneously but at the cost of increased area. Algorithmic optimization techniques have also been used which includes exclusion of shift row stage and on the fly round key generation. The corresponding hardware realization is optimal in terms of area and offers high data throughout. An optimized code for the implementation of Rijndael algorithm for 128 bits has been developed and experimentally tested using Xilinx Virtex XC2VP70-7 device. A 119.954 MHz clock frequency is achieved which translates to a throughput of 1.18 Gbps using 6279 Slices and 5 BRAMs. The design handles both encryption and decryption and fits into a single FPGA.