Power minimization of rotary clock design

Rotary clock is a recently proposed clock distribution technique based on wave propagation in transmission lines. In this paper, we present the first design methodology to minimize the power dissipation of rotary clock structures. Specifically, our scheme derives a rotary clock array that dissipates minimal power while satisfying the clock dimension requirement and oscillating at the target frequency with the given clock load. Experimental results have demonstrated that, for designs with operating frequencies ranging from 0.5 to 5 Gigahertz, our approach achieves a 24.3% power reduction on the average compared with power-unaware design methods. Furthermore, rotary clock designs implemented using our scheme consume as low as 31% power of the optimal conventional clock tree designs