Thermal-aware mapping and placement for 3-D NoC designs

Author

Addo-Quaye, Charles

Author_Institution

Pennsylvania State Univ., University Park, PA

fYear

2005

fDate

19-23 Sept. 2005

Firstpage

25

Lastpage

28

Abstract

Networks on chip (NoC) and 3D integrated circuits have been proposed as solutions to the ever-growing interconnect woes surrounding systems-on-chip. 3D designs however suffer from hotspot creation, due to the increase in the power density of parts of the chip. In this paper, we propose the use of a genetic algorithm for a thermal and communication aware mapping and placement of application tasks on 3D NoC environment. Our results show a significant reduction in system temperature when compared to a random mapping and placement, and provide an encouraging situation for migration to the 3D design space

Keywords

circuit optimisation; genetic algorithms; integrated circuit design; integrated circuit interconnections; network-on-chip; 3D NoC designs; 3D integrated circuits; communication aware mapping; genetic algorithm; networks on chip; systems-on-chip; thermal-aware mapping; Algorithm design and analysis; Energy efficiency; Genetic algorithms; Integrated circuit interconnections; Iterative algorithms; Network-on-a-chip; Stacking; Telecommunication network reliability; Temperature; Three-dimensional integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2005. Proceedings. IEEE International

Conference_Location

Herndon, VA

Print_ISBN

0-7803-9264-7

Type

conf

DOI

10.1109/SOCC.2005.1554447

Filename

1554447