Investigation on RF Characteristics of Stacked P-I-N Polysilicon Diodes for ESD Protection Design in 0.18-μm CMOS Technology

Author

Shiu, Yu-Da ; Chuang, Che-Hao ; Ker, Ming-Dou

Author_Institution

SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu

fYear

2006

fDate

24-26 April 2006

Firstpage

1

Lastpage

4

Abstract

An ESD protection design by using the stacked p-i-n polysilicon diodes for CMOS RF integrated circuits is proposed to reduce the input capacitance and to avoid the noise coupling from the common substrate. In this paper, the dc I-V characteristics, RF S-parameters, and ESD robustness of the stacked p-i-n polysilicon diodes are investigated in a 0.18-mum salicided CMOS process. This polysilicon diode with small parasitic capacitance and high ESD robustness is fully process compatible to general CMOS process without extra process modification

Keywords

CMOS integrated circuits; S-parameters; electrostatic discharge; p-i-n diodes; radiofrequency integrated circuits; 0.18 micron; CMOS RF integrated circuits; CMOS technology; ESD protection design; I-V characteristics; RF characteristics; S-parameters; parasitic capacitance; polysilicon diodes; stacked p-i-n diodes; CMOS process; CMOS technology; Electrostatic discharge; Integrated circuit noise; Noise robustness; P-i-n diodes; PIN photodiodes; Parasitic capacitance; Protection; Radio frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2006 International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

1-4244-0181-4

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2006.251064

Filename

4016600