Novel VLSI architecture of motion estimation for H.264 standard

Author

Li, Xiang ; Chopra, Rahul ; Hsu, Kenneth W.

Author_Institution

Rochester Inst. of Technol., NY, USA

fYear

2005

fDate

25-28 Sept. 2005

Firstpage

117

Lastpage

118

Abstract

A novel architecture to achieve real-time motion estimation compensation encoding for H.264 ITU video compression standard is presented. A full-search block matching algorithm has been adapted to a pipelined data flow to enable parallel processing of variable block sized block matching and fractional pixel motion vector generation. The SOC is designed with TSMC 0.18μm technology using VHDL and optimized to achieve a 125 MHz clock speed to make real-time processing possible.

Keywords

VLSI; data compression; integrated circuit design; motion estimation; pipeline processing; real-time systems; system-on-chip; video coding; 0.18 micron; 125 MHz; H.264 standard; VLSI architecture; fractional pixel motion vector generation; full-search block matching algorithm; parallel processing; pipelined data flow; real-time motion estimation compensation encoding; variable block sized block matching; video compression standard; Automatic voltage control; Bandwidth; Bit rate; Encoding; Motion compensation; Motion estimation; Telecommunication standards; Transform coding; Very large scale integration; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2005. Proceedings. IEEE International

Print_ISBN

0-7803-9264-7

Type

conf

DOI

10.1109/SOCC.2005.1554476

Filename

1554476