ATPG for ultra-large structured designs

Author

Waicukauski, John A. ; Shupe, Paul A. ; Giramma, David J. ; Matin, Arshad

Author_Institution

Mentor Graphics Corp., Beaverton, OR, USA

fYear

1990

fDate

10-14 Sep 1990

Firstpage

44

Lastpage

51

Abstract

A ATPG (automatic test pattern generation) system that can efficiently create a high-coverage test for extremely large scan designs is described. This system is formed by optimally combining a fast fault simulator with a powerful test generator. For the ISCAS85 and ISCAS89 circuits, this ATPG system created a test for all testable faults and identified all redundant faults without a single aborted fault. This represents the first time this has been achieved for the ISCAS89 designs, and the performance of this ATPG system is significantly better than published results. Performing ATPG for the largest ISCAS89 designs, which contained about 25000 gates, required only 3 min of CPU time on an Apollo DN3550 workstation. The data collected for the ISCAS designs showed that the ATPG CPU time increased linearly with gate count. This strongly suggests that ATPG can be efficiently performed for circuits of 100000 and even one million gates

Keywords

automatic test equipment; automatic testing; fault location; logic testing; ATPG CPU time; Apollo DN3550 workstation; ISCAS85; ISCAS89; automatic test pattern generation; fault simulator; gate count; high-coverage test; large scan designs; redundant faults; test generator; ultra-large structured designs; Automatic test pattern generation; Automatic testing; Central Processing Unit; Circuit faults; Circuit simulation; Circuit testing; Fault diagnosis; Power generation; System testing; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1990. Proceedings., International

Conference_Location

Washington, DC

Print_ISBN

0-8186-9064-X

Type

conf

DOI

10.1109/TEST.1990.113999

Filename

113999