Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routing

Because of the continuous increase in transistor count, interconnect complexity, and operating frequencies of system-on-chip (SoC) designs, power and area have become critical issues. Power, noise, and area reduction of soft intellectual property (IP) cores using a low-overhead wave-pipelined multiplexed (WPM) interconnect routing technique is proposed. Using system-level simulation, it is shown that the application of WPM routing decreases power by 14% and core area by 28% for a core area-centric design, and for a wire coupling-centric design, power reduces by 6% and wire coupling by 20%