An architecture for high-speed analog in-circuit testing

Conventional analog in-circuit tests run considerably slower than digital ones, putting throughput at risk as circuit boards incorporate more analog components. The authors describe a novel architecture in which distributed processors work in parallel to dramatically speed analog testing. This architecture uses distributed digital-signal-processing chips operating independently and in parallel to achieve a sevenfold improvement in analog in-circuit test throughput over conventional test approaches. Design efforts concentrated on efficient use of the distributed processors in handling matrix-resource allocation and all analog test functions, and on minimizing physical effects that could inhibit test speed