DocumentCode
2724135
Title
The ERSO 1.2 μm standard cell design system
Author
Chang, W.Y. ; Fong, R.H. ; Lou, C.C. ; Lee, H.C. ; Liang, Y.A. ; Hsieh, J.C. ; Chang, L.C. ; Huang, P.S. ; Lee, R.C.
Author_Institution
Electron. Res. & Service Organ., Hsing-Chu, Taiwan
fYear
1989
fDate
17-19 May 1989
Firstpage
183
Lastpage
187
Abstract
A 1.2-μm standard-cell design system has been designed for system-level integration. It contains 200 primitive SSI (small-scale integration) cells, 53 soft-coded MSI (medium-scale integration) cells, and compilable RAM (random-access memory), ROM (ready-only memory), and PLA (programmable logic array). Four chips-a 12500-gate-count enhanced video graphic array (EVGA), a SSI, and MSI, and a compilable cell test chip-have been designed to verify the design system
Keywords
cellular arrays; logic arrays; logic design; random-access storage; read-only storage; 1.2 micron; ERSO; PLA; ROM; SSI; compilable RAM; enhanced video graphic array; soft-coded MSI; standard cell design system; system-level integration; Capacitance; Circuit simulation; Equations; Libraries; Logic testing; Propagation delay; Routing; System testing; Temperature; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Conference_Location
Taipei
Type
conf
DOI
10.1109/VTSA.1989.68610
Filename
68610
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