Advanced CMOS protection device trigger mechanisms during CDM

Author

Duvvury, Charvaka ; Amerasekera, Ajith

Author_Institution

Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA

fYear

1995

fDate

12-14 Sept. 1995

Firstpage

162

Lastpage

174

Abstract

The Charged Device Model (CDM) is now considered to be an important stress model for defining ESD reliability of IC chips. This paper examines the CDM performance for three different advanced protection devices in a 0.35 /spl mu/m LDD CMOS technology. Through failure analysis and device simulations, the behavior of these protection devices during the CDM event is investigated. The results will enable devices to be designed for improved CDM protection levels.

Keywords

CMOS integrated circuits; electrostatic discharge; failure analysis; integrated circuit modelling; integrated circuit reliability; protection; 0.35 micron; CDM protection levels; CMOS protection devices; ESD reliability; IC chips; LDD CMOS technology; advanced protection devices; charged device model; device simulations; failure analysis; protection device trigger mechanisms; stress model; Analytical models; CMOS technology; Discrete event simulation; Electrostatic discharge; Failure analysis; Integrated circuit modeling; Protection; Semiconductor device modeling; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1995

Conference_Location

Phoenix, AZ, USA

Print_ISBN

1-878303-59-7

Type

conf

DOI

10.1109/EOSESD.1995.478281

Filename

478281