Experimental validation of parallel computation models on the Intel Paragon

Author

Juurlink, Ben H H

Author_Institution

Heinz Nixdorf Inst., Paderborn Univ., Germany

fYear

1998

fDate

30 Mar-3 Apr 1998

Firstpage

492

Lastpage

497

Abstract

Experimental data validating some of the proposed parallel computation models on the Intel Paragon is presented. This architecture is characterized by a large bandwidth and a relatively large startup cost of a message transmission, which makes it extremely important to employ bulk transfers. The models considered are the BSP model, in which it is assumed that all messages have a fixed short size, and the BPRAM, in which block transfers are rewarded

Keywords

message passing; parallel machines; BPRAM; BSP model; Intel Paragon; architecture; block transfers; bulk transfers; experimental validation; fixed short size messages; large bandwidth; large startup cost; message transmission; parallel computation models; Bandwidth; Computational modeling; Computer architecture; Concurrent computing; Costs; Libraries; Parallel architectures; Phase change random access memory; Predictive models; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Processing Symposium, 1998. IPPS/SPDP 1998. Proceedings of the First Merged International ... and Symposium on Parallel and Distributed Processing 1998

Conference_Location

Orlando, FL

ISSN

1063-7133

Print_ISBN

0-8186-8404-6

Type

conf

DOI

10.1109/IPPS.1998.669961

Filename

669961

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2727530