A 14 b 150 Msample/s update rate Q/sup 2/ random walk CMOS DAC

Current steering DACs are based on an array of matched current cells organized in unary decoded or binary weighted elements. The segmented architecture is most frequently used to combine high conversion rate and high resolution. In this architecture the least significant bits steer binary weighted current sources, while the most significant bits are thermometer decoded and steer a unary current source array. The limitations of these architectures in terms of accuracy, linearity (INL) and speed are technology dependent. A modified segmented DAC architecture and a switching scheme, called Q/sup 2/ random walk, overcome the technology constraints.