A 500 MHz 1.5 MB cache with on-chip CPU

Author

Lachman, J. ; Hill, J.M.

Author_Institution

Hewlett-Packard Co., Fort Collins, CO, USA

fYear

1999

fDate

17-17 Feb. 1999

Firstpage

192

Lastpage

193

Abstract

The access time, latency, and yield of embedded caches limit present generation processors to incorporate approximately 128 kB of memory. This 1.8 ns access time four-way-set-associative on-chip 1 MB data cache (D-cache) and 1.6 ns access time four-way-set-associative on-chip 0.5 MB instruction cache (I-cache) allow single-cycle access with up to three stores or loads executed every cycle. The caches communicate with the CPU over two 64 b data busses and a 128 b instruction bus running at the processor clock frequency of 500 MHz for 16 GB/s total effective bandwidth.

Keywords

cache storage; clocks; embedded systems; integrated circuit yield; microprocessor chips; 1.5 MB; 1.6 ns; 1.8 ns; 128 bit; 500 MHz; 64 bit; D-cache; I-cache; access time; data cache; embedded caches; four-way-set-associative on-chip cache; instruction bus; instruction cache; latency; on-chip CPU; processor clock frequency; single-cycle access; total effective bandwidth; yield; Bandwidth; CMOS technology; Circuit testing; Clocks; Decoding; Delay; Field-flow fractionation; Frequency; Logic; Pulse amplifiers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-5126-6

Type

conf

DOI

10.1109/ISSCC.1999.759189

Filename

759189