Hot-Carrier Reliability of NLDEMOS in 0.13μm SOI CMOS Technology

Author

Lachenal, D. ; Rey-Tauriac, Y. ; Boissonnet, L. ; Reynard, B. ; Bravaix, A.

Author_Institution

STMicroelectronics, Crolles

fYear

2006

fDate

3-7 July 2006

Firstpage

80

Lastpage

83

Abstract

This paper presents reliability investigations in NLDEMOS transistor in 0.13μm SOI CMOS technology. Reliability tests under hot carrier injections (HCI) for different gate-lengths show two different degradation mechanisms. The modification of current path with short overlap (O_lap) due to oblique equi-potential lines and the increase in the vertical electrical field under the gate edge at low V _g lead to distinguish N_it interface trap generation from the source side injection

Keywords

CMOS integrated circuits; MOSFET; hot carriers; interface states; semiconductor device reliability; silicon-on-insulator; 0.13 micron; CMOS; NLDEMOS transistor; SOI; degradation mechanisms; hot carrier injections; hot carrier reliability; interface trap generation; reliability tests; CMOS technology; Condition monitoring; Degradation; Hot carriers; Human computer interaction; MOSFETs; Radio frequency; Stress; Testing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2006. 13th International Symposium on the

Conference_Location

Singapore

Print_ISBN

1-4244-0205-0

Electronic_ISBN

1-4244-0206-9

Type

conf

DOI

10.1109/IPFA.2006.251002

Filename

4017027