αΩHighway interconnection network architecture for high performance computing

The interconnection network is a crucial part of high-performance computer systems. It significantly determines parallel system performance as well as the development and the operating cost. In this paper we suggest efficient and scalable hierarchical multi-ring interconnection network architecture. For building up the interconnection network we have designed adequate switch architecture and implemented “step-back-on-blocking” flow control algorithm. The architectural model has been verified and communicational performance parameters have been evaluated on the basis of numerous simulation experiments conducted in the OMNeT++ simulation environment.