A single-chip CIF 30 Hz H261, H263, and H263+ video encoder/decoder with embedded display controller

Several videophone codecs have already been reported, some of them using a more hardware oriented architecture, some of them using a more software oriented one. The evolution of video compression standards for videophony implies more and more complex algorithms, with more and more coding options: no option for H261, 4 in H263, 15 in H263+. Software implementations provide the flexibility required by this trend. However, this evolution is also more and more demanding in processing power, and low cost is a major factor in this market. Therefore, this chip has a mixed hardware/software architecture to combine performance and flexibility. Performance is needed for simultaneous coding and decoding of 30 CIF (288/spl times/352) frames per second with <1.5 W consumption, while flexibility is needed to track the evolution of standards from H261 and H263 (all options) to H263+, gaining in image quality and bit rate.