DocumentCode
2729679
Title
Inductance Considerations of on-Chip Interconnections for Best Electrostatic Discharge Protection Performance
Author
Sofer, Sergey ; Fefer, Yefim ; Shapira, Yoram
Author_Institution
Freescale Semicond. Israel Ltd., Herzelia
fYear
2006
fDate
3-7 July 2006
Firstpage
158
Lastpage
162
Abstract
The inductance of the on-die interconnection lines may cause voltage resonant effects under electrostatic discharge (ESD) stress. The phase difference of the resonating oscillations along different ESD current flow paths creates a significant local momentary voltage. Information on this inductance enables designers to take into consideration these voltage resonant effects in ESD protection design
Keywords
electrostatic discharge; inductance; integrated circuit design; integrated circuit interconnections; system-on-chip; electrostatic discharge protection; inductance considerations; on-chip interconnections; resonating oscillations; voltage resonant effects; Clamps; Electrostatic discharge; Inductance; Integrated circuit interconnections; MOSFET circuits; Protection; Resonance; Semiconductor device manufacture; Stress; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical and Failure Analysis of Integrated Circuits, 2006. 13th International Symposium on the
Conference_Location
Singapore
Print_ISBN
1-4244-0205-0
Electronic_ISBN
1-4244-0206-9
Type
conf
DOI
10.1109/IPFA.2006.251020
Filename
4017045
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