Ultra-low power Digital System Design using Sub-threshold logic styles

The paper shows the implementation of digital circuit design using ultra-low power logic components. Fundamentals of Source coupled logic (SCL) gates are used with running at sub-threshold regime with the purpose of achieving low power consumption while keeping a satisfactory output swing. The digital system designed for this paper are 4-by-4 array multiplier and a fifty-fifth order FIR filter. The paper also includes modification of an STSCL (sub-threshold source coupled logic) inverter by adding controllable voltage-level feature to it, in order to minimize overall leakage current flow, including both gate and sub-threshold leakage. The modified STSCL inverter has been tested and simulated on a seven-stage ring oscillator design. The rest of the results for the designed digital systems are obtained by separate implementation of the circuits with CMOS and STSCL respectively. Simulations have been performed at similar supply voltage to observe the differences in power consumption. Consumption for the proposed technique came at nW range. All measurements are shown for both 45 nm and 65 nm process technology, with scaling of the supply voltage to an achievable minimum value of 0.4 V.