DocumentCode
2730008
Title
Bond Pad Optimization for CMOS Imager with Chip Scale Package
Author
Rassel, R.J. ; Guthrie, W. ; Gambino, J. ; Maloney, J.J. ; Stidham, M. ; Sprogis, E. ; Adkisson, J.W. ; Jaffe, M.
Author_Institution
IBM Microelectron., Essex Junction, VT
fYear
2006
fDate
3-7 July 2006
Firstpage
235
Lastpage
238
Abstract
Three novel CSP pad designs in a 0.18mum CMOS image sensor Cu interconnect technology were analyzed for use with a wafer level CSP (WLCSP) package. The CSP pad designs used various combinations of available aluminum and tungsten interconnect levels in order to improve the cross-sectional area without increasing the total stack height of the Cu interconnect technology. It was found that by increasing the cross-sectional area of the CSP pads the T-connections formed in the CSP process had improved (tighter) resistance distributions
Keywords
CMOS image sensors; chip scale packaging; copper; integrated circuit interconnections; 0.18 micron; CMOS image sensor; Cu; bond pad optimization; interconnect technology; wafer level chip scale package; Bonding; CMOS image sensors; CMOS technology; Chip scale packaging; Copper; Dielectrics; Integrated circuit interconnections; Optical sensors; Wafer scale integration; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical and Failure Analysis of Integrated Circuits, 2006. 13th International Symposium on the
Conference_Location
Singapore
Print_ISBN
1-4244-0205-0
Electronic_ISBN
1-4244-0206-9
Type
conf
DOI
10.1109/IPFA.2006.251037
Filename
4017062
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