A 755 Mb/s Viterbi decoder for the RM (64, 35, 8) subcode

As speed demands in broadband communication systems increase into the Gb/s region, economical implementation of robust high-speed soft-decision error-correcting decoders becomes necessary. Convolutional codes are one approach that have been widely employed in communication and storage systems. Decoders for convolutional codes have trellis structures and are typically decoded using the Viterbi algorithm. The speed of these decoders is limited by the well-known add-compare-select (ACS) bottleneck. In addition, previously reported decoder implementations use a radix-4 ACS block which processes two symbols per clock cycle. An alternative to convolutional codes are block codes which also have trellis structures that can be decoded using the Viterbi algorithm. Since trellises for block codes have well-defined source and destination states, bi-directional decoding which overcomes the ACS bottleneck states can be employed. Furthermore, processing eight or more symbols per clock cycle becomes practical allowing manageable system clock frequencies in high rate decoders. This paper describes a Viterbi decoder IC for the Reed-Muller (RM) (64,35,8) subcode.