Pb-free solder joint reliability of fine pitch chip-scale packages

Chip-scale package (CSP) is commonly seen on high density boards as it minimizes the foot print while packed more functionality into one component. Board level reliability concern over CSPs is that finer pitch limits the solder ball size attached and the stencil thickness used in assembly which leads to much smaller joint volume and standoff while larger die-to-package ratio typically means higher stress level caused by the CTE mismatch. Prior studies have shown that the grain orientation may impact SnAgCu solder joint reliability. With less solder volume, the joint reliability of fine pitch SnAgCu solder may be more sensitive to the grain size, grain orientation, and IMC formation within the bulk solder. The purpose of the study is to evaluate the board level reliability of Pb-free ball grid array (BGA) packages with ball pitch smaller than 0.5mm under different packaging and assembly conditions. Based on a test vehicle with 0.4mm pitch daisy-chained CVBGA, the impact on solder joint reliability from a wide spectrum of variables such as PCB thickness, SMT configuration, die size, package pad finish, and mini cycle profiling has been investigated. The results of this study enable us to better understand the Pb-free fine pitch joint behaviors under different conditions and the factors that have significant impact on joint reliability. Isothermal aging effect has also been studied, will be presented in a separated paper, which demonstrated that isothermal aging could significantly degrade joint reliability for fine pitch packages. The ATC results proved that the fine pitch packages may underperform the components with regular 0.8–1.0mm pitch therefore extra attention needs to be paid on fine pitch components while converting high reliability products to Pb-free.