DocumentCode
273324
Title
An approach to fast hierarchical fault simulation
Author
Motohara, Akira ; Murakami, Motohide ; Urano, Miki ; Masuda, Yasuo ; Sugano, Masahide
Author_Institution
Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
fYear
1988
fDate
12-15 June 1988
Firstpage
698
Lastpage
703
Abstract
The authors present an approach to hierarchical fault simulation which generates several simulation models of one circuit and carries out simulation for each. Fault insertion and simulation-model generation is done automatically. Switch-level simulation which utilizes lookup tables is as fast as gate-level simulation. Experimental results show that using behavioral description and switch-level truth tables is effective in improving simulation speed.<>
Keywords
circuit analysis computing; logic CAD; table lookup; behavioral description; fault insertion; hierarchical fault simulation; logic design environment; lookup tables; simulation-model generation; switch-level truth tables; CMOS logic circuits; CMOS technology; Circuit faults; Circuit simulation; Computational modeling; Computer simulation; Delay; Semiconductor device modeling; Sequential circuits; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location
Anaheim, CA, USA
ISSN
0738-100X
Print_ISBN
0-8186-0864-1
Type
conf
DOI
10.1109/DAC.1988.14845
Filename
14845
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