Minimizing minimum delay compensations for timing variation-aware datapath synthesis

As the feature size of transistors becomes smaller, delay variations become a serious problem in VLSI design. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. One approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). This paper is the first attempt to discuss an optimization problem to minimize the number of FUs which require MDC in datapath synthesis. One of our contributions is to show that the problem is NP-hard in general, and it is in the class P if the number of FUs is a constant. In addition, a polynomial time algorithm for the latter is another contribution. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.