DocumentCode
2734176
Title
Flexible decoder architectures for irregular QC-LDPC codes
Author
Kuo, Tzu-chieh ; Willson, Alan N.
Author_Institution
Dept. of Electr. Eng., Univ. of California, Los Angeles, CA
fYear
2008
fDate
10-13 Aug. 2008
Firstpage
229
Lastpage
232
Abstract
A flexible and power-efficient decoder architecture employing the layered-decoding message-passing algorithm and the low-complexity offset-based Min-Sum check algorithm for irregular QC-LDPC codes is presented in this paper. The architecture is verified by implementing a programmable decoder chip compliant with the QC-LDPC codes in Mobile WiMAX standard. Compared to other published decoder implementations, the prototype decoder is 53% smaller and has better energy efficiency.
Keywords
WiMax; broadband networks; error correction codes; parity check codes; radio access networks; Mobile WiMAX standard; flexible decoder architectures; irregular QC-LDPC codes; layered-decoding message-passing algorithm; low-complexity offset-based Min-Sum check algorithm; programmable decoder chip; Application specific integrated circuits; Code standards; Decoding; Energy efficiency; Joining processes; Parity check codes; Prototypes; USA Councils; Very large scale integration; WiMAX;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on
Conference_Location
Knoxville, TN
ISSN
1548-3746
Print_ISBN
978-1-4244-2166-4
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2008.4616778
Filename
4616778
Link To Document