DocumentCode
2734402
Title
Realization of multi-level partial response modem in reconfigurable logic
Author
Pienaar, J.F. ; Linde, L.P. ; Marx, F.E.
Author_Institution
Dept. of Electr., Electron. & Comput. Eng., Pretoria Univ., South Africa
Volume
1
fYear
2002
fDate
2-4 Oct. 2002
Firstpage
167
Abstract
Hardware realization is an important issue in communications system design. The use of high density reconfigurable logic instead of traditional DSP based solutions is investigated. The case of a multi-level partial response modem is discussed. The practical logic structures of the internal modem components including equalizer, Viterbi decoder and FIR filters are presented. Results of the hardware implementation are also presented.
Keywords
FIR filters; Viterbi decoding; digital filters; equalisers; logic circuits; modems; FIR filters; Viterbi decoder; communications system design; equalizer; hardware realization; high density reconfigurable logic; multi-level partial response modem; Application specific integrated circuits; Costs; Digital signal processing; Digital signal processing chips; Field programmable gate arrays; Finite impulse response filter; Hardware; Logic design; Modems; Reconfigurable logic;
fLanguage
English
Publisher
ieee
Conference_Titel
Africon Conference in Africa, 2002. IEEE AFRICON. 6th
Print_ISBN
0-7803-7570-X
Type
conf
DOI
10.1109/AFRCON.2002.1146827
Filename
1146827
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