Estimate of the Power Dissipation of Multilayer and High Density Nano-CMOS Chip

The structure model of the multilayer and high density nano-CMOS chip is described. Based on the power dissipation of nano-CMOS transistors, the fitting curve of the devices number of the chip device layer with average surface density of power dissipation, as concerns heat removed easily, the formula of power dissipation of multilayer and high density nano-CMOS chip is deduced. The power dissipation of a nano-CMOS transistor (P_trt), a device layer (P_cl), and the chip (P_ct) are estimated. The calculation results are reliable, and the conclusions of estimation contribute to the thermal design and the cooling of electronic package. In the design of the multilayer and high density CMOS chip, the maximum power dissipation layer is placed nearest heat sink is proposed. So far as soft design of the chip, the optimization of power dissipation should be considered under satisfying functions