A test chip for CPAL register file fabricated in chartered 0.35μm CMOS process

A 32 times 32 register file based on complementary pass-transistor adiabatic logic (CPAL) has been fabricated with chartered 0.35 mum process. All the circuits except for the storage cells employ CPAL circuits. The storage cell is based on the conventional memory one. For comparison, a conventional 32 times 32 register file is also embedded in the chip. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. The results show the CPAL register file can work very well, and it attains 57% energy saves than the conventions register file at 100 MHz.