• DocumentCode
    2735147
  • Title

    System validation by source level emulation of behavioral VHDL specifications

  • Author

    Koch, Gernot ; Kebschull, Udo ; Rosenstiel, Wolfgang

  • Author_Institution
    Forschungszentrum Inf., Karlsruhe, Germany
  • fYear
    1995
  • fDate
    7-9 Jun 1995
  • Firstpage
    210
  • Lastpage
    216
  • Abstract
    We present an approach to accelerate the validation speed of behavioral VHDL system specifications through the use of hardware emulation. The method allows source level debugging of behavioral, algorithmic VHDL in a way similar to source level debugging known from software programming languages. We can set breakpoints in the source code and evaluate the contents of variables by reading the registers of the circuit when a breakpoint is reached
  • Keywords
    circuit analysis computing; hardware description languages; logic CAD; logic design; program debugging; program verification; algorithmic VHDL; behavioral VHDL specifications; breakpoints; hardware emulation; source level debugging; source level emulation; system validation; Acceleration; Circuits; Emulation; Formal verification; Hardware; High level synthesis; Registers; Software algorithms; Software debugging; Superluminescent diodes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Rapid System Prototyping, 1995. Proceedings., Sixth IEEE International Workshop on
  • Conference_Location
    Chapel Hill, NC
  • ISSN
    1074-6005
  • Print_ISBN
    0-8186-7100-9
  • Type

    conf

  • DOI
    10.1109/IWRSP.1995.518593
  • Filename
    518593
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2735147