Signal integrity characterization and modelling of a PCI/PCI-x 66/133 MHz bus

Author

Sharawi, Mohammad S.

Author_Institution

Comput. Eng. Dept., Philadelphia Univ., Amman

fYear

2008

fDate

10-13 Aug. 2008

Firstpage

490

Lastpage

493

Abstract

Design and characterization of high speed digital buses and interconnects is an essential part in the computer hardware development process. Signal Integrity (SI) testing and verification examines the signal levels, shapes and timing requirements against specifications. In this work, we present a full SI characterization and modelling of a peripheral component interconnect (PCI) bus as well as a PCI-extended (PCI-x) bus running at 66 MHz/133 MHz, respectively. Laboratory measurements show the compliance with specification timing and signal levels.

Keywords

logic testing; peripheral interfaces; system buses; PCI bus; PCI-extended bus; PCI-x bus; computer hardware development; frequency 133 MHz; frequency 66 MHz; high speed digital buses; high speed digital interconnects; peripheral component interconnect bus; signal integrity characterization; signal integrity modelling; signal integrity testing; Bandwidth; Ethernet networks; Hardware; Laboratories; Packaging; Shape; Signal design; Signal processing; Switches; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on

Conference_Location

Knoxville, TN

ISSN

1548-3746

Print_ISBN

978-1-4244-2166-4

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2008.4616843

Filename

4616843