60Gb/s low jitter 4:1 Mux and 1:4 DeMux

Author

Luo, Yifei ; Chen, Gang ; Zhou, Kuan

Author_Institution

Dept. Electr. & Comput. Eng., New Hampshire Univ., Durham, NH

fYear

2008

fDate

10-13 Aug. 2008

Firstpage

590

Lastpage

593

Abstract

4:1 multiplexers (Muxs) and 1:4 demultiplexers (DeMuxs) are always the bottleneck in the GHz serializer/deserializer (SerDes) implementation. This paper discusses the design of the 60 Gb/s 4:1 Mux and 1:4 DeMux with the 0.18 mum silicon germanium (SiGe) BiCMOS technology. The Mux and DeMux are controlled by a quarter clock that significantly reduces the clock frequency and relaxes the circuit design requirement. Several design techniques, such as inductive peaking and delay matching, are used in this paper to push forward the maximum data transfer rate. The output jitter of the Mux is approximately 2.2 ps. The power consumptions of the Mux and DeMux are 140 mW and 85 mW respectively.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; demultiplexing equipment; jitter; multiplexing equipment; 1:4 demultiplexers; 4:1 multiplexers; BiCMOS technology; GHz serializer/deserializer implementation; SerDes implementation; SiGe; bit rate 60 Gbit/s; clock frequency; delay matching; inductive peaking; output jitter; power 140 mW; power 85 mW; quarter clock; size 0.18 mum; BiCMOS integrated circuits; Circuit synthesis; Clocks; Delay; Energy consumption; Frequency; Germanium silicon alloys; Jitter; Multiplexing; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on

Conference_Location

Knoxville, TN

ISSN

1548-3746

Print_ISBN

978-1-4244-2166-4

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2008.4616868

Filename

4616868