Implementation of two dimensional forward DCT and inverse DCT using FPGA

Author

Mohd-Yusof, Zulkalnain ; Suleiman, Ish ; Aspar, Zulfakar

Author_Institution

Fac. of Electr. Eng., Univ. Technol. Malaysia, Johor Bahru, Malaysia

Volume

3

fYear

2000

fDate

2000

Firstpage

242

Abstract

This paper describes the (field programmable gate array) FPGA implementation of two dimensional forward and inverse discrete cosine transform (2D-DCT and 2D-IDCT) using the 100 K gate ALTERA FLEX10K100 FPGA/CPLD. The architecture used in both 2D-DCT and 2D-IDCT is based on the conventional row-column decomposition method. The use of a fast algorithm and distributed arithmetic (DA) technique to implement the DCT and IDCT greatly reduces the hardware complexity

Keywords

data compression; discrete cosine transforms; distributed arithmetic; field programmable gate arrays; image coding; inverse problems; matrix decomposition; transform coding; video coding; 2D DCT; 2D IDCT; 2D forward DCT; 2D inverse DCT; ALTERA FLEX10K100 FPGA/CPLD; FPGA implementation; discrete cosine transform; distributed arithmetic; fast algorithm; field programmable gate array; hardware complexity reduction; image compression standards; row-column decomposition method; video compression standards; Arithmetic; Clocks; Discrete Fourier transforms; Discrete cosine transforms; Field programmable gate arrays; Frequency; Hardware; Image coding; Transform coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 2000. Proceedings

Conference_Location

Kuala Lumpur

Print_ISBN

0-7803-6355-8

Type

conf

DOI

10.1109/TENCON.2000.892266

Filename

892266