• DocumentCode
    2735892
  • Title

    Technology mapping with layout constraints

  • Author

    Zanden, N.V. ; Wu, C. H Allen ; Gajski, Daniel

  • Author_Institution
    Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
  • fYear
    1989
  • fDate
    17-19 May 1989
  • Firstpage
    227
  • Lastpage
    231
  • Abstract
    An examination is made of how logic synthesis systems can incorporate layout parameters to better meet designer constraints. The author define an algorithm and present a synthesis tool for technology mapping with custom layout generators. Experimental results indicate that such an approach produces faster and denser layouts and permits greater area/time tradeoffs than traditional logic synthesis systems
  • Keywords
    circuit layout; logic design; area/time tradeoffs; custom layout generators; denser layouts; designer constraints; layout parameters; logic synthesis systems; synthesis tool; technology mapping; Chip scale packaging; Computer science; Constraint optimization; Design optimization; Libraries; Logic arrays; Logic design; Parasitic capacitance; Productivity; Routing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
  • Conference_Location
    Taipei
  • Type

    conf

  • DOI
    10.1109/VTSA.1989.68619
  • Filename
    68619
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2735892