Joint coding for RLC coupling-aware on-chip buses

As technology scales, inductive crosstalk becomes prominent along with capacitive crosstalk, and it is creating a significant bottleneck in high-speed deep sub-micron and nanoscale integrated circuits. For inductive coupling, worst-case delay occurs when all the bus lines simultaneously switch in the same direction. This switching case is the best case switching pattern for capacitive-dominant on-chip buses. Therefore, various existing coding techniques for capacitive crosstalk reduction are not suitable for high-speed circuits, where electromagnetic effect can not be ignored. In this paper, various hybrid bus-invert (BI) coding methods have been proposed for RLC coupling-aware on-chip buses. Simulation results show that simultaneous switching noise (SSN) for inductance-dominant buses can be reduced by roughly 40% and, thereby, worst case coupling delay is also reduced. Besides, a joint coding approach is proposed for simultaneous reduction of SSN and higher reliability to errors due to deep-submicron (DSM) noise.