A 6-Gbps/pin Half-Duplex LVDS I/O for High-Speed Mobile DRAM

This paper presents a high-speed LVDS I/O interface for mobile DRAMs. A data rate of 6Gbps/pin and a transmit-jitter of 57.31ps pk-pk were demonstrated, in which an 800MHz clock and a 200mV swing were used. The power consumption by I/O circuit is 6.2mW/pin when a 10pf load is connected to the I/O, and output supply voltage is 1.2V. The proposed mobile DRAM has 6 data pins and 4 address/command pins for a multi-chip package (MCP). The transmitter uses a feed-back LVDS output driver and a common-mode feed-back controller achieving the reduction of driver currents and the constant common-mode as half voltage level. To achieve a low-transmit jitter, we use a driver with a double step pre-emphasis. The receiver employs a shared preamplifier scheme, which ensures transmit power reduction. The proposed DRAM with LVDS I/O was fabricated using an 80-nm DRAM process. It exhibits 161.1mV times 150ps rms eye-windows on the given channel