An automatic router for the pin grid array package

Author

Chen, Shuenn-Shi ; Chen, Jong-Jang ; Chen, Sao-Jie ; Tsai, Chia-Chun

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1999

fDate

18-21 Jan 1999

Firstpage

133

Abstract

A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment topological routing, and geometrical routing. Examples tested on a windows-based environment show that our router is efficient and can complete the routing task with less substrate layers. Compared to manual routing, this router features a friendly graphic user interface and can be practically applied to VLSI packaging

Keywords

VLSI; circuit layout CAD; graphical user interfaces; integrated circuit packaging; network routing; network topology; GUI; PGA package router; VLSI packaging; automatic router; geometrical routing; graphic user interface; layer assignment topological routing; pad-to-pin nets; pin grid array package; planar interconnection; windows-based environment; Crosstalk; Electronics packaging; Graphics; Integrated circuit interconnections; Integrated circuit packaging; Pins; Routing; Testing; User interfaces; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Conference_Location

Wanchai

Print_ISBN

0-7803-5012-X

Type

conf

DOI

10.1109/ASPDAC.1999.759783

Filename

759783