Physical analysis of the high-temperature subthreshold slope in SOI MOSFETs

Conventional bulk silicon CMOS circuits can operate only at moderate temperatures (up to 150-200°C). At higher temperatures, bulk silicon CMOS devices usually fail because of increased junction leakage, thermally induced latchup, and threshold voltage shift. Thanks to the high-temperature advantages of SOI MOSFETs, the range of SOI CMOS operation can be extended up to 300°C (Francis et al, 1992; Flandre et al, 1993; Eggermont et al, 1996). To better understand device behavior, it is necessary to reconsider the physics of the SOI MOSFET at high temperatures. In this work, we revise the validity of the classical expression for the subthreshold swing and analyze the physics behind the temperature degradation of the subthreshold slope in both thick- and thin-film SOI MOSFETs