Sub-micron fully depleted lateral asymmetric channel SOI MOSFETs for analog and mixed mode applications

Recently, communication and other advanced applications have driven the development of system-on-a-chip (SOC) technology. Due to its rapid advances, fully depleted (FD) SOI CMOS is a very promising candidate for mixed mode and analog circuits (Flandre et al, 1999). In addition to potentially superior device performance, the SOI substrate provides much better device isolation, which is crucial for SOC applications. In the deep submicron regime, the lateral asymmetric channel (LAC) structures have shown better control of the short channel effects (SCE) such as V_th roll-off, and DIBL LAC devices also have higher current drive by exploiting the velocity overshoot phenomenon which is advantageous for high performance digital applications (Cheng et al, 1999). For analog applications, the device transconductance (g_m), the intrinsic gain (g_mR_out) and the low frequency noise performance are other important parameters. In this paper, the LAC devices are compared with conventional devices in the submicron regime down to L_drawn of 0.2 μm for analog and mixed mode applications