Performance improvements in high-density DRAM application using 0.15 μm body-contacted SOI technology

Author

Lee, Jong-Wook ; Kim, Hyung-Ki ; Kim, Jong-Soo ; Lee, Won-Chang ; Oh, Jeong-Hee ; Kang, Dae-Gwan ; Koh, Yo-Hwan

Author_Institution

Div. for Memory R&D, Hyundai Electron. Ind. Co., Kyoungki-do, South Korea

fYear

2000

fDate

2000

Firstpage

76

Lastpage

77

Abstract

A 0.15 μm silicon-on-insulator (SOI) CMOS technology, using a body-contacted (BC) SOI structure, is developed. This process technology is fully compatible with bulk CMOS technology except for the isolation process. The key advantage of the BC-SOI MOSFET is that it is free from floating-body effects, since the body-potential increase can be suppressed by the well contact through the remaining thin-silicon film beneath the shallow trench isolation. This technology was applied to 256 Mbit SOI SDRAM, which shows improved refresh characteristics compared with bulk devices

Keywords

CMOS memory circuits; DRAM chips; MOSFET; SRAM chips; integrated circuit measurement; isolation technology; silicon-on-insulator; 0.15 micron; 256 Mbit; BC-SOI MOSFET; SOI CMOS technology; SOI SDRAM; Si-SiO₂; body-contacted SOI structure; body-contacted SOI technology; body-potential increase suppression; bulk CMOS technology compatibility; floating-body effects; high-density DRAM application; isolation process; process technology; refresh characteristics; shallow trench isolation; silicon-on-insulator CMOS technology; thin-silicon film; well contact; CMOS technology; Capacitance; Capacitors; Isolation technology; Leakage current; MOSFET circuits; Random access memory; Research and development; Silicon on insulator technology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2000 IEEE International

Conference_Location

Wakefield, MA

ISSN

1078-621X

Print_ISBN

0-7803-6389-2

Type

conf

DOI

10.1109/SOI.2000.892777

Filename

892777