Proposal of sub 0.1 μm SOI MOSFET structure (partial-ground-plane SOI MOSFET) for RF/digital applications

It is considered that for RF applications, bipolar transistors and compound semiconductor devices are superior to conventional MOSFETs from the viewpoints of high-frequency operation and noise characteristics (Barlas et al., 1999; Hwang et al., 1999; Tseng and Ye, 1999). Bipolar transistors, however, have base current loss and more complexity in terms of device miniaturization; compound semiconductor devices need complex fabrication processes with high material costs (Bollaert et al., 1999). It is known that the double-gate (DG) SOI MOSFET and the ground-plane (GP) SOI MOSFET offer high immunity against short-channel effects (SCE) (Wong et al., 1986). This paper proposes an interesting device structure that can realize 0.05 μm channel devices. DC, switching, and RF characteristics of the proposed structure are simulated in a comparison to conventional SG and GP devices