A novel 4T SRAM cell using `self-body-biased” SOI MOSFET structure operating at 0.5 volt

Author

Terauchi, Mamoru

Author_Institution

Dept. of Comput. Eng., Hiroshima City Univ., Japan

fYear

2000

fDate

2000

Firstpage

108

Lastpage

109

Abstract

A novel 4T SRAM cell utilizing the `self-body-biased´ (`SBB´) SOI MOSFET structure (Terauchi and Terada, Proc. IEEE Int. SOI Conf., p. 36, 1999) is proposed. The body region of an SOI MOSFET with an `H-shaped´ gate electrode is used as a resistor in the inverter pair of the SRAM cell. The resistance of the body region is controlled by the low impurity concentration region beneath the auxiliary gate electrode and its geometry, independently from the threshold voltage of the MOSFET. Device simulation reveals the stable operation of the proposed SRAM cell under supply voltage of as low as 0.5 V

Keywords

CMOS memory circuits; MOSFET; SRAM chips; circuit simulation; circuit stability; electric resistance; electrodes; impurity distribution; integrated circuit modelling; logic gates; semiconductor device models; silicon-on-insulator; 0.5 V; 4T SRAM cell; CMOS fabrication processes; H-shaped gate electrode resistor; SOI MOSFET body region; SRAM cell inverter pair; Si-SiO₂; auxiliary gate electrode; body region resistance; device simulation; low impurity concentration region; operating voltage; self-body-biased SOI MOSFET structure; stable operation; supply voltage; threshold voltage; Body regions; Electrodes; Geometry; Immune system; Impurities; Inverters; MOSFET circuits; Random access memory; Resistors; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2000 IEEE International

Conference_Location

Wakefield, MA

ISSN

1078-621X

Print_ISBN

0-7803-6389-2

Type

conf

DOI

10.1109/SOI.2000.892793

Filename

892793