Diagnosing single faults for interconnects in SRAM based FPGAs

Author

Yu, Yinlei ; Xu, Jian ; Huang, Wei Kang ; Lombardi, Fabrizio

Author_Institution

ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China

fYear

1999

fDate

18-21 Jan 1999

Firstpage

283

Abstract

This paper presents a method to diagnose faults in FPGA interconnection resources. A single fault model is given. Under the given model, a diagnosing method is proposed. At most five programming steps in the proposed method is required if adaptive testing scheme is used. For non-adaptive test, eight programming steps is required to diagnose all the possible faults under the given single fault model. The accuracy of the fault diagnosing is one segment for a segment stuck-at or stuck-open fault, a segment pair for a bridge fault, a switch for switch stuck-on or stuck-off fault

Keywords

SRAM chips; automatic testing; fault diagnosis; field programmable gate arrays; integrated circuit interconnections; integrated circuit testing; logic testing; FPGA; SRAM; adaptive testing; bridge fault; interconnects; programming; segment pair; single fault model; single faults; stuck-at fault; stuck-off fault; stuck-open fault; switch stuck-on; Application specific integrated circuits; Bridges; Circuit faults; Field programmable gate arrays; Integrated circuit interconnections; Laboratories; Logic programming; Logic testing; Random access memory; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Conference_Location

Wanchai

Print_ISBN

0-7803-5012-X

Type

conf

DOI

10.1109/ASPDAC.1999.760014

Filename

760014