High responsivity CMOS imager pixel implemented in SOI technology

The availability of mature sub-micron CMOS technology and the advent of low noise active pixel sensors (APS) enabled the development of low power, miniature single-chip CMOS digital imagers in the 1990s. The primary advantages of CMOS APS include low cost, low power (100-1000× lower than CCDs), simple digital interface, random access, simplicity of operation (single CMOS compatible power supply), high speed, miniaturization, radiation hardness, and smartness by incorporating on-chip signal processing circuits. However, there are several limitations in implementing CMOS imagers in deep sub-μm technology. Reduction in depletion length needed for implementing sub-μm MOSFETs and the reduction in epitaxial silicon thickness cause reduction in quantum efficiency (QE) and increased pixel-to-pixel crosstalk due to collection of photo-generated electrons through diffusion over the field-free region. Furthermore, beyond 0.25 μm CMOS technology, the use of SOI technology seems imminent. Typical SOI designs use 40-200 nm thick silicon films, which is too small to provide adequate photon absorption in the visible spectrum. Hence, SOI technology is generally considered to be incompatible with CMOS imager implementation. However, the key to achieving high photo-response is to implement the photodiode in the SOI substrate (also called the “handle-wafer”), while the thin SOI-film is used to implement only the FETs necessary for pixel readout